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constexpr auto | address () const noexcept -> u64 |
| | Extract the page-aligned translation-exception address.
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constexpr auto | asce_id () const noexcept -> u64 |
| | Extract the ASCE identifier ( bits 62-63).
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constexpr auto | fsi_raw () const noexcept -> u64 |
| | Extract the AEFSI fetch/store indication.
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constexpr auto | is_fetch () const noexcept -> bool |
| | True if AEFSI says the access was an instruction fetch.
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constexpr auto | is_side_effect () const noexcept -> bool |
| | True if bit 54 (side-effect-access indication) is set.
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constexpr auto | is_store () const noexcept -> bool |
| | True if AEFSI says the access was a store.
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constexpr auto | protection_is_alc () const noexcept -> bool |
| | True if the protection code reported by basic SOP / ESOP-1 indicates access-list-controlled (ALC) protection.
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constexpr auto | protection_is_exec () const noexcept -> bool |
| | True if the 3-bit protection code (bits 56, 60, 61) decodes to 101.
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u64 : 1 | |
| | bit 55 — unpredictable.
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u64 : 3 | |
| | bits 57-59 — unpredictable.
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u64 addr: 52 | |
| | bits 0-51 — translation-exception address.
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u64 as: 2 | |
| | bits 62-63 — ASCE identifier.
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u64 b56: 1 | |
| | bit 56 — protection-code bit 0 (ESOP-2).
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u64 b60: 1 | |
| | bit 60 — protection-code bit 1 / ALC indication.
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u64 b61: 1 | |
| | bit 61 — protection-code bit 2 / MOVE PAGE / TEID remainder.
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u64 fsi: 2 | |
| | bits 52-53 — Access-Exc Fetch/Store Indication.
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u64 sea: 1 | |
| | bit 54 — side-effect access (use is_side_effect()).
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u64 | val |
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constexpr u8 | arch::s390x::cpu::teid::ADDR_LSB_OFF = 12 |
| | bit-position helpers.
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constexpr u8 | arch::s390x::cpu::teid::FSI_LSB_OFF = 10 |
| | bits 52-53 (Access-Exc Fetch/Store).
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constexpr u8 | arch::s390x::cpu::teid::SE_LSB_OFF = 9 |
| | bit 54 (side-effect access).
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constexpr u8 | arch::s390x::cpu::teid::B56_LSB_OFF = 7 |
| | bit 56 (protection-code bit 0).
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constexpr u8 | arch::s390x::cpu::teid::B60_LSB_OFF = 3 |
| | bit 60 (protection-code bit 1 / ALC).
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constexpr u8 | arch::s390x::cpu::teid::B61_LSB_OFF = 2 |
| | bit 61 (protection-code bit 2 / MOVE PAGE).
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constexpr u8 | arch::s390x::cpu::teid::AS_LSB_OFF = 0 |
| | bits 62-63 (ASCE identifier).
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constexpr u64 | arch::s390x::cpu::teid::TEID_FSI_UNKNOWN = 0 |
| | Access-Exception Fetch/Store Indication (AEFSI) — TEID bits 52-53.
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constexpr u64 | arch::s390x::cpu::teid::TEID_FSI_STORE = 1 |
| | 01 — store-type access.
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constexpr u64 | arch::s390x::cpu::teid::TEID_FSI_FETCH = 2 |
| | 10 — instruction-fetch access.
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_PRIMARY = 0 |
| | ASCE identifier encoding (TEID bits 62-63).
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_AR = 1 |
| | 01 — access-register mode (AR-specified).
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_SECONDARY = 2 |
| | 10 — secondary ASCE.
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_HOME = 3 |
| | 11 — home ASCE.
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constexpr u8 | arch::s390x::cpu::teid::ADDR_LSB_OFF = 12 |
| | bit-position helpers.
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constexpr u8 | arch::s390x::cpu::teid::FSI_LSB_OFF = 10 |
| | bits 52-53 (Access-Exc Fetch/Store).
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constexpr u8 | arch::s390x::cpu::teid::SE_LSB_OFF = 9 |
| | bit 54 (side-effect access).
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constexpr u8 | arch::s390x::cpu::teid::B56_LSB_OFF = 7 |
| | bit 56 (protection-code bit 0).
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constexpr u8 | arch::s390x::cpu::teid::B60_LSB_OFF = 3 |
| | bit 60 (protection-code bit 1 / ALC).
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constexpr u8 | arch::s390x::cpu::teid::B61_LSB_OFF = 2 |
| | bit 61 (protection-code bit 2 / MOVE PAGE).
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constexpr u8 | arch::s390x::cpu::teid::AS_LSB_OFF = 0 |
| | bits 62-63 (ASCE identifier).
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constexpr u64 | arch::s390x::cpu::teid::TEID_FSI_UNKNOWN = 0 |
| | Access-Exception Fetch/Store Indication (AEFSI) — TEID bits 52-53.
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constexpr u64 | arch::s390x::cpu::teid::TEID_FSI_STORE = 1 |
| | 01 — store-type access.
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constexpr u64 | arch::s390x::cpu::teid::TEID_FSI_FETCH = 2 |
| | 10 — instruction-fetch access.
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_PRIMARY = 0 |
| | ASCE identifier encoding (TEID bits 62-63).
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_AR = 1 |
| | 01 — access-register mode (AR-specified).
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_SECONDARY = 2 |
| | 10 — secondary ASCE.
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constexpr u64 | arch::s390x::cpu::teid::TEID_AS_HOME = 3 |
| | 11 — home ASCE.
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