z/Architecture control register store/load/set/clear wrappers. More...

import lib.bit;
import lib.bitfield;
import zxfoundation.base.types;

Include dependency graph for ctlreg.cxxm:

Data Structures
struct	arch::s390x::cpu::ctlreg::home_asce_extension< T >
struct	arch::s390x::cpu::ctlreg::primary_asce_extension< T >
struct	arch::s390x::cpu::ctlreg::secondary_asce_extension< T >

Typedefs
using	arch::s390x::cpu::ctlreg::cr0
using	arch::s390x::cpu::ctlreg::cr0_view
using	arch::s390x::cpu::ctlreg::cr1
using	arch::s390x::cpu::ctlreg::cr10
using	arch::s390x::cpu::ctlreg::cr10_view
using	arch::s390x::cpu::ctlreg::cr11
using	arch::s390x::cpu::ctlreg::cr11_view
using	arch::s390x::cpu::ctlreg::cr12
using	arch::s390x::cpu::ctlreg::cr12_view
using	arch::s390x::cpu::ctlreg::cr13
using	arch::s390x::cpu::ctlreg::cr13_view
using	arch::s390x::cpu::ctlreg::cr14
using	arch::s390x::cpu::ctlreg::cr14_view
using	arch::s390x::cpu::ctlreg::cr15
using	arch::s390x::cpu::ctlreg::cr15_view
using	arch::s390x::cpu::ctlreg::cr1_view
using	arch::s390x::cpu::ctlreg::cr2
using	arch::s390x::cpu::ctlreg::cr2_view
using	arch::s390x::cpu::ctlreg::cr3
using	arch::s390x::cpu::ctlreg::cr3_view
using	arch::s390x::cpu::ctlreg::cr4
using	arch::s390x::cpu::ctlreg::cr4_view
using	arch::s390x::cpu::ctlreg::cr5
using	arch::s390x::cpu::ctlreg::cr5_view
using	arch::s390x::cpu::ctlreg::cr6
using	arch::s390x::cpu::ctlreg::cr6_view
using	arch::s390x::cpu::ctlreg::cr7
using	arch::s390x::cpu::ctlreg::cr7_view
using	arch::s390x::cpu::ctlreg::cr8
using	arch::s390x::cpu::ctlreg::cr8_view
using	arch::s390x::cpu::ctlreg::cr9
using	arch::s390x::cpu::ctlreg::cr9_view

Enumerations
enum class	asce_type : u8 { region_table_destination = 0 , segment_table_destination = 1 , real_space_destination = 3 }

Functions
template<u32 Low, u32 High, typename T> requires (Low <= 15 && High <= 15 && Low <= High && sizeof(T) >= (High - Low + 1) * 8)
auto	arch::s390x::cpu::ctlreg::crread (T &storage) noexcept -> void
	Store control registers [Low..High] into a storage area (STCTG).
template<u32 Low, u32 High, typename T> requires (Low <= 15 && High <= 15 && Low <= High && sizeof(T) >= (High - Low + 1) * 8)
auto	arch::s390x::cpu::ctlreg::crwrite (const T &storage) noexcept -> void
	Load control registers [Low..High] from a storage area (LCTLG).

Detailed Description

z/Architecture control register store/load/set/clear wrappers.

SPDX-License-Identifier: Apache-2.0

Typedef Documentation

◆ cr1

using arch::s390x::cpu::ctlreg::cr1

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::extensions<primary_asce_extension>,
        lib::rw<"primary_origin", lib::bits<0, 51>>,
        lib::rw<"primary_subspace_group_ctl", lib::bits<54, 54>>,
        lib::rw<"primary_private_space_ctl", lib::bits<55, 55>>,
        lib::rw<"primary_storage_alter_event_ctl", lib::bits<57, 57>>,
        lib::rw<"primary_real_space_ctl", lib::bits<58, 58>>,
        lib::rw<"primary_degsination_type_ctl", lib::bits<60, 61>>,
        lib::rw<"primary_table_length", lib::bits<62, 63>>
    >

◆ cr10

using arch::s390x::cpu::ctlreg::cr10

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"per_starting_address", lib::bits<0, 63>>
    >

◆ cr10_view

using arch::s390x::cpu::ctlreg::cr10_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"per_starting_address", lib::bits<0, 63>>
    >

◆ cr11

using arch::s390x::cpu::ctlreg::cr11

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"per_ending_address", lib::bits<0, 63>>
    >

◆ cr11_view

using arch::s390x::cpu::ctlreg::cr11_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"per_ending_address", lib::bits<0, 63>>
    >

◆ cr12

using arch::s390x::cpu::ctlreg::cr12

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"branch_trace_ctl", lib::bits<0, 0>>,
        lib::rw<"mode_trace_ctl", lib::bits<1, 1>>,
        lib::rw<"trace_entry_address", lib::bits<2, 61>>,
        lib::rw<"asn_trace_ctl", lib::bits<62, 62>>,
        lib::rw<"explicit_trace_ctl", lib::bits<63, 63>>
    >

◆ cr12_view

using arch::s390x::cpu::ctlreg::cr12_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"branch_trace_ctl", lib::bits<0, 0>>,
        lib::rw<"mode_trace_ctl", lib::bits<1, 1>>,
        lib::rw<"trace_entry_address", lib::bits<2, 61>>,
        lib::rw<"asn_trace_ctl", lib::bits<62, 62>>,
        lib::rw<"explicit_trace_ctl", lib::bits<63, 63>>
    >

◆ cr13

using arch::s390x::cpu::ctlreg::cr13

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::extensions<home_asce_extension>,
        lib::rw<"home_origin", lib::bits<0, 51>>,
        lib::rw<"home_subspace_group_ctl", lib::bits<54, 54>>,
        lib::rw<"home_private_space_ctl", lib::bits<55, 55>>,
        lib::rw<"home_storage_alter_event_ctl", lib::bits<57, 57>>,
        lib::rw<"home_real_space_ctl", lib::bits<58, 58>>,
        lib::rw<"home_degsination_type_ctl", lib::bits<60, 61>>,
        lib::rw<"home_table_length", lib::bits<62, 63>>
    >

◆ cr13_view

using arch::s390x::cpu::ctlreg::cr13_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::extensions<home_asce_extension>,
        lib::rw<"home_origin", lib::bits<0, 51>>,
        lib::rw<"home_subspace_group_ctl", lib::bits<54, 54>>,
        lib::rw<"home_private_space_ctl", lib::bits<55, 55>>,
        lib::rw<"home_storage_alter_event_ctl", lib::bits<57, 57>>,
        lib::rw<"home_real_space_ctl", lib::bits<58, 58>>,
        lib::rw<"home_degsination_type_ctl", lib::bits<60, 61>>,
        lib::rw<"home_table_length", lib::bits<62, 63>>
    >

◆ cr14

using arch::s390x::cpu::ctlreg::cr14

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"extended_save_area_ctl", lib::bits<34, 34>>,
        lib::rw<"channel_report_pending_subclass_mask", lib::bits<35, 35>>,
        lib::rw<"recovery_subclass_mask", lib::bits<36, 36>>,
        lib::rw<"degradation_subclass_mask", lib::bits<37, 37>>,
        lib::rw<"external_damage_subclass_mask", lib::bits<38, 38>>,
        lib::rw<"warning_subclass_mask", lib::bits<39, 39>>,
        lib::rw<"tod_clock_control_override_ctl", lib::bits<42, 42>>,
        lib::rw<"asn_translation_ctl", lib::bits<44, 44>>,
        lib::rw<"asn_first_table_origin", lib::bits<45, 63>>
    >

◆ cr14_view

using arch::s390x::cpu::ctlreg::cr14_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"extended_save_area_ctl", lib::bits<34, 34>>,
        lib::rw<"channel_report_pending_subclass_mask", lib::bits<35, 35>>,
        lib::rw<"recovery_subclass_mask", lib::bits<36, 36>>,
        lib::rw<"degradation_subclass_mask", lib::bits<37, 37>>,
        lib::rw<"external_damage_subclass_mask", lib::bits<38, 38>>,
        lib::rw<"warning_subclass_mask", lib::bits<39, 39>>,
        lib::rw<"tod_clock_control_override_ctl", lib::bits<42, 42>>,
        lib::rw<"asn_translation_ctl", lib::bits<44, 44>>,
        lib::rw<"asn_first_table_origin", lib::bits<45, 63>>
    >

◆ cr15

using arch::s390x::cpu::ctlreg::cr15

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"linkage_stack_entry_address", lib::bits<0, 60>>
    >

◆ cr15_view

using arch::s390x::cpu::ctlreg::cr15_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"linkage_stack_entry_address", lib::bits<0, 60>>
    >

◆ cr1_view

using arch::s390x::cpu::ctlreg::cr1_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::extensions<primary_asce_extension>,
        lib::rw<"primary_origin", lib::bits<0, 51>>,
        lib::rw<"primary_subspace_group_ctl", lib::bits<54, 54>>,
        lib::rw<"primary_private_space_ctl", lib::bits<55, 55>>,
        lib::rw<"primary_storage_alter_event_ctl", lib::bits<57, 57>>,
        lib::rw<"primary_real_space_ctl", lib::bits<58, 58>>,
        lib::rw<"primary_degsination_type_ctl", lib::bits<60, 61>>,
        lib::rw<"primary_table_length", lib::bits<62, 63>>
    >

◆ cr2

using arch::s390x::cpu::ctlreg::cr2

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"dispatch_unit_ctl_table_origin", lib::bits<33, 57>>,
        lib::rw<"guarded_stor_fac_enablement_ctl", lib::bits<59, 59>>,
        lib::rw<"transaction_diagnostic_scope", lib::bits<61, 61>>,
        lib::rw<"transaction_diagnostic_ctl", lib::bits<62, 63>>
    >

◆ cr2_view

using arch::s390x::cpu::ctlreg::cr2_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
       lib::rw<"dispatch_unit_ctl_table_origin", lib::bits<33, 57>>,
       lib::rw<"guarded_stor_fac_enablement_ctl", lib::bits<59, 59>>,
       lib::rw<"transaction_diagnostic_scope", lib::bits<61, 61>>,
       lib::rw<"transaction_diagnostic_ctl", lib::bits<62, 63>>
   >

◆ cr3

using arch::s390x::cpu::ctlreg::cr3

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"secondary_asn_instance_num", lib::bits<0, 31>>,
        lib::rw<"psw_key_mask", lib::bits<32, 47>>,
        lib::rw<"secondary_asn", lib::bits<48, 63>>
    >

◆ cr3_view

using arch::s390x::cpu::ctlreg::cr3_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"secondary_asn_instance_num", lib::bits<0, 31>>,
        lib::rw<"psw_key_mask", lib::bits<32, 47>>,
        lib::rw<"secondary_asn", lib::bits<48, 63>>
    >

◆ cr4

using arch::s390x::cpu::ctlreg::cr4

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"primary_asn_instance_num", lib::bits<0, 31>>,
        lib::rw<"auth_index", lib::bits<32, 47>>,
        lib::rw<"parimary_asn", lib::bits<48, 63>>
    >

◆ cr4_view

using arch::s390x::cpu::ctlreg::cr4_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"primary_asn_instance_num", lib::bits<0, 31>>,
        lib::rw<"auth_index", lib::bits<32, 47>>,
        lib::rw<"parimary_asn", lib::bits<48, 63>>
    >

◆ cr5

using arch::s390x::cpu::ctlreg::cr5

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"primary_asn_origin", lib::bits<33, 57>>
    >

◆ cr5_view

using arch::s390x::cpu::ctlreg::cr5_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"primary_asn_origin", lib::bits<33, 57>>
    >

◆ cr6

using arch::s390x::cpu::ctlreg::cr6

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"io_interruption_ssm", lib::bits<32, 39>>
    >

◆ cr6_view

using arch::s390x::cpu::ctlreg::cr6_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"io_interruption_ssm", lib::bits<32, 39>>
    >

◆ cr7

using arch::s390x::cpu::ctlreg::cr7

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::extensions<secondary_asce_extension>,
        lib::rw<"secondary_origin", lib::bits<0, 51>>,
        lib::rw<"secondary_subspace_group_ctl", lib::bits<54, 54>>,
        lib::rw<"secondary_private_space_ctl", lib::bits<55, 55>>,
        lib::rw<"secondary_storage_alter_event_ctl", lib::bits<57, 57>>,
        lib::rw<"secondary_real_space_ctl", lib::bits<58, 58>>,
        lib::rw<"secondary_degsination_type_ctl", lib::bits<60, 61>>,
        lib::rw<"secondary_table_length", lib::bits<62, 63>>
    >

◆ cr7_view

using arch::s390x::cpu::ctlreg::cr7_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::extensions<secondary_asce_extension>,
        lib::rw<"secondary_origin", lib::bits<0, 51>>,
        lib::rw<"secondary_subspace_group_ctl", lib::bits<54, 54>>,
        lib::rw<"secondary_private_space_ctl", lib::bits<55, 55>>,
        lib::rw<"secondary_storage_alter_event_ctl", lib::bits<57, 57>>,
        lib::rw<"secondary_real_space_ctl", lib::bits<58, 58>>,
        lib::rw<"secondary_degsination_type_ctl", lib::bits<60, 61>>,
        lib::rw<"secondary_table_length", lib::bits<62, 63>>
    >

◆ cr8

using arch::s390x::cpu::ctlreg::cr8

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"enhanced_monitor_masks", lib::bits<16, 31>>,
        lib::rw<"extended_auth_index", lib::bits<32, 47>>,
        lib::rw<"monitor_masks", lib::bits<48, 63>>
    >

◆ cr8_view

using arch::s390x::cpu::ctlreg::cr8_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"enhanced_monitor_masks", lib::bits<16, 31>>,
        lib::rw<"extended_auth_index", lib::bits<32, 47>>,
        lib::rw<"monitor_masks", lib::bits<48, 63>>
    >

◆ cr9

using arch::s390x::cpu::ctlreg::cr9

export

Initial value:

 lib::record<u64, lib::msb0_t,
        lib::rw<"successful_branching_event_mask", lib::bits<32, 32>>,
        lib::rw<"instruction_fetching_event_mask", lib::bits<33, 33>>,
        lib::rw<"storage_alteration_event_mask", lib::bits<34, 34>>,
        lib::rw<"storage_key_alteration_event_mask", lib::bits<35, 35>>,
        lib::rw<"store_using_real_address_event_mask", lib::bits<36, 36>>,
        lib::rw<"zero_address_detection_event_mask", lib::bits<37, 37>>,
        lib::rw<"transaction_end_event_mask", lib::bits<38, 38>>,
        lib::rw<"instruction_fetching_nullification_event_mask", lib::bits<39, 39>>,
        lib::rw<"branch_address_ctl", lib::bits<40, 40>>,
        lib::rw<"per_event_suppression_ctl", lib::bits<41, 41>>,
        lib::rw<"storage_alteration_space_ctl", lib::bits<42, 42>>
    >

◆ cr9_view

using arch::s390x::cpu::ctlreg::cr9_view

export

Initial value:

 lib::record_ref<u64, lib::msb0_t,
        lib::rw<"successful_branching_event_mask", lib::bits<32, 32>>,
        lib::rw<"instruction_fetching_event_mask", lib::bits<33, 33>>,
        lib::rw<"storage_alteration_event_mask", lib::bits<34, 34>>,
        lib::rw<"storage_key_alteration_event_mask", lib::bits<35, 35>>,
        lib::rw<"store_using_real_address_event_mask", lib::bits<36, 36>>,
        lib::rw<"zero_address_detection_event_mask", lib::bits<37, 37>>,
        lib::rw<"transaction_end_event_mask", lib::bits<38, 38>>,
        lib::rw<"instruction_fetching_nullification_event_mask", lib::bits<39, 39>>,
        lib::rw<"branch_address_ctl", lib::bits<40, 40>>,
        lib::rw<"per_event_suppression_ctl", lib::bits<41, 41>>,
        lib::rw<"storage_alteration_space_ctl", lib::bits<42, 42>>
    >

Function Documentation

◆ crread()

template<u32 Low, u32 High, typename T>
requires (Low <= 15 && High <= 15 && Low <= High && sizeof(T) >= (High - Low + 1) * 8)

auto arch::s390x::cpu::ctlreg::crread ( T & storage ) ->void

exportnoexcept

Store control registers [Low..High] into a storage area (STCTG).

Template Parameters

Low	Starting control register index (0–15).
High	Ending control register index (0–15), must be ≥ Low.
T	Storage type; sizeof(T) must cover (High-Low+1) × 8 bytes.

Parameters

storage Output buffer to receive the register values.

◆ crwrite()

template<u32 Low, u32 High, typename T>
requires (Low <= 15 && High <= 15 && Low <= High && sizeof(T) >= (High - Low + 1) * 8)

auto arch::s390x::cpu::ctlreg::crwrite ( const T & storage ) ->void

exportnoexcept

Load control registers [Low..High] from a storage area (LCTLG).

Template Parameters

Low	Starting control register index (0–15).
High	Ending control register index (0–15), must be ≥ Low.
T	Storage type; sizeof(T) must cover (High-Low+1) × 8 bytes.

Parameters

storage Input buffer containing the new register values.

ZXFoundation™ 26h2

Data Structures

Typedefs

Enumerations

Functions

Detailed Description

Typedef Documentation

◆ cr1

◆ cr10

◆ cr10_view

◆ cr11

◆ cr11_view

◆ cr12

◆ cr12_view

◆ cr13

◆ cr13_view

◆ cr14

◆ cr14_view

◆ cr15

◆ cr15_view

◆ cr1_view

◆ cr2

◆ cr2_view

◆ cr3

◆ cr3_view

◆ cr4

◆ cr4_view

◆ cr5

◆ cr5_view

◆ cr6

◆ cr6_view

◆ cr7

◆ cr7_view

◆ cr8

◆ cr8_view

◆ cr9

◆ cr9_view

Function Documentation

◆ crread()

◆ crwrite()