arch::s390x::cpu::teid::teid Union Reference

Union view of a 64-bit TEID. More...

Public Member Functions
constexpr auto	address () const noexcept -> u64
	Extract the page-aligned translation-exception address.
constexpr auto	asce_id () const noexcept -> u64
	Extract the ASCE identifier ( bits 62-63).
constexpr auto	fsi_raw () const noexcept -> u64
	Extract the AEFSI fetch/store indication.
constexpr auto	is_fetch () const noexcept -> bool
	True if AEFSI says the access was an instruction fetch.
constexpr auto	is_side_effect () const noexcept -> bool
	True if bit 54 (side-effect-access indication) is set.
constexpr auto	is_store () const noexcept -> bool
	True if AEFSI says the access was a store.
constexpr auto	protection_is_alc () const noexcept -> bool
	True if the protection code reported by basic SOP / ESOP-1 indicates access-list-controlled (ALC) protection.
constexpr auto	protection_is_exec () const noexcept -> bool
	True if the 3-bit protection code (bits 56, 60, 61) decodes to 101.

Data Fields
struct {
u64   : 1
	bit 55 — unpredictable.
u64   : 3
	bits 57-59 — unpredictable.
u64   addr: 52
	bits 0-51 — translation-exception address.
u64   as: 2
	bits 62-63 — ASCE identifier.
u64   b56: 1
	bit 56 — protection-code bit 0 (ESOP-2).
u64   b60: 1
	bit 60 — protection-code bit 1 / ALC indication.
u64   b61: 1
	bit 61 — protection-code bit 2 / MOVE PAGE / TEID remainder.
u64   fsi: 2
	bits 52-53 — Access-Exc Fetch/Store Indication.
u64   sea: 1
	bit 54 — side-effect access (use is_side_effect()).
};
u64	val

Detailed Description

Union view of a 64-bit TEID.

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The documentation for this union was generated from the following file:

• arch/s390x/cpu/teid.cxxm